This invention relates to a standard cell type semiconductor integrated circuit having function and cell blocks.
In general, standard cell type LSIs are advantageously used for forming semicustom-built LSIs. When, for example, a function block such as RAM or ROM having a data storing function, or a multiplier having a calculating function is formed on an LSI chip, it is formed in such a pattern as is shown in FIG. 1. That is, the function block includes VDD power source wiring layer 61 and VSS power source wiring layer 62 which are each formed of aluminum, as first or lower wiring layers, in a comb-like shape, with their tooth portions alternately arranged. Element regions (ER) 63 are defined by the adjacent tooth portions of wiring layers 61 and 62. In order to connect wiring layers 61 and 62 of the function block to power source wiring layers of a cell block adjacent to the function block, some tooth portions are extended to form power source nodes such as VDD nodes 64A and VSS nodes 65A, and the remaining tooth portions are electrically coupled, via second or upper wiring layers 66, to power source connection nodes 64B and 65B which are formed of the first wiring layers in positions facing the remaining tooth portions.
FIG. 2 shows an example of the connection pattern connecting the power source wiring layers of the function block to the power source wiring layers of the cell block formed on the same chip. The cell block has a plurality of column areas each including a set made up of VDD wiring layer 71 VSS wiring layer 72, element region 73 located therebetween, and wiring regions (WR) 74 In the case where the width of wiring region 74 of the cell block is equal to that of element region 73, and the number of wiring layers 71 and 72 is equal to that of the wiring layers or the tooth portions of the function block, the VDD and VSS wiring layers of the cell block can be respectively connected to the VDD and VSS wiring layers of the function block via power source wiring connection layers constituted by lower layers 75. In this case, the VDD or VSS wiring layer of the cell and function blocks connected by connection layer 75 can be arranged in a straight line.
The width of wiring region 74 in the cell block may vary depending on the wiring pattern design, the number of the wiring layers in the cell block not always being equal to that of the wiring layers or comb tooth portions in the function block. Therefore, in the case where the width of wiring region 74 is reduced and the number of wiring layers in the cell block is increased, some cell column areas of the cell block cannot then be connected to the power source wiring layers of the function block, as is shown by the wiring pattern in FIG. 3. Further, part of power source wiring connection layer will extend into the signal wiring area, as is shown by portion A. A cell column area which cannot be connected to the function block is much less able to supply power source current as compared with the other cell column areas which are connected to the function block, with the result that standard cells in the former cell column area may operate erroneously. Further, when the power source wiring connection layer extends partly into the signal wiring area, as described before, the wiring efficiency will be lowered. When power source nodes 64A, 64B, 65A, and 65B are arranged at fixed positions on the function block, it may then become difficult to connect the function block and cell block to each other, on the same chip, by means of a simple form of power source wiring connection pattern. That is, with the positions of the power source nodes fixed, the form of the wiring connection pattern will likely become more complicated.